1. Field of the Invention
The present invention relates to bus encoding and decoding, and more particularly to encoding and decoding of discontinuous bus data.
2. Description of Related Art
In a computer system, various devices transmit data among each other through buses. The data passes through the bus at an extremely high rate, such that the status of bus lines is rapidly converted between 0 and 1. The bus line transition between 0 and 1 results in charging or discharging of bus wires, and the capacitance value of a system bus is hundreds of times of, even thousands of times of, that of an internal logic circuit. Therefore, the bus is highly power-consuming in the system, and the power consumed during data transmission is substantially in direct proportion to the number of bus line bit-transitions.
For the purpose of power saving, the number of bus line bit-transitions must be reduced, and the most efficient way is bus encoding. As long as a receiver decodes the transmitted data correctly, a transmitter can encode the data into forms that result in fewer bus line bit-transitions. Taking an instruction address bus which transmits instruction addresses for example. Since most program instructions are sequentially executed, consecutive addresses appear on the bus. The encoder may apply Gray Code to make the consecutive addresses differ form each other for only one bit after encoding, thereby greatly reducing the electricity consumed by data transmission.
However, the bus transmits not only consecutive data, but also discontinuous data. For example, branch instructions might cause instruction addresses being discontinuous. Up to the present, various technologies have been developed to encode consecutive bus data to reduce the the number of bus line bit-transitions, such as Gray Code, Zero-Transition (T0), and burst mode. However, we still needs a solution to encode discontinuous bus data to reduce the the number of bus line bit-transitions.